The present invention generally relates to integrated circuit (IC) chips that are interconnected by metal interconnect lines to a substrate supporting the chips. More particularly, this invention relates to a method and structure for reducing thermally-induced mechanical shear stresses in an IC chip in the vicinity where such metal lines are electrically connected to the chip.
FIG. 1 represents an integrated circuit (IC) chip 12 for a microwave high density interconnect (HDI) module 10 such as shown in U.S. Pat. No. 5,355,102 to Kornrumpf et al. The chip 12 is shown as being mounted within a recess 13 formed in a surface of a substrate 14, which may be a ceramic substrate, printed wiring board, flexible circuit, or a silicon substrate. A dielectric material, such as a polymer, is shown as being deposited on the substrate 14 and chip 12 to form a dielectric layer 16 that bridges a xe2x80x9cmoatxe2x80x9d 15 surrounding the chip 12. The dielectric layer 16 may be a first of any number of dielectric layers that separate the substrate 14 and subsequent metallized layers of the module 10.
The chip 12 is electrically connected with circuitry on the substrate 14 with metal interconnect lines 18 formed on the dielectric layer 16. Each line 18 is individually interconnected with a contact pad 20 on the chip 12 through a via 22 formed in the dielectric layer 16. As shown, the contact pads 20 are typically located in a peripheral surface region 26 of the chip 12 near its perimeter 24. The pads 20 are formed of an electrically-conductive metal and are electrically interconnected with the chip surface circuitry 28. Due to the numerous functions typically performed by the microcircuitry of the chip 12, multiple lines 18 are typically required. The size of the chip 12 can be on the order of a few millimeters per side or less, resulting in the contact pads 20 being crowded along the chip perimeter 24.
One of the required steps for microwave HDI processes is a large area ablation (LAA) of the dielectric layer 16 on the active area 28 of the chip 12. Because of the presence of the lines 18, the dielectric layer 16 remains over the peripheral surface region 26 of the chip 12, including the contact pads 20. It has been observed that once the dielectric layer 16 is removed from the active area 28, the edges of the chip 12 are prone to fracturing in the vicinity of the interconnect lines 18, as depicted in FIG. 2. Fractures 30 of the type represented in FIG. 2 generally occur during thermal cycling, particularly during the cooling cycle. Delamination of the contact pads 20 has also been observed.
It would be desirable to eliminate or at least reduce the likelihood of chip fracture and pad delamination of the type described above. To be practical, a solution would preferably not require special equipment, exotic materials or complex processing steps. While thermally-induced stresses would appear to be the primary influence in initiating the observed damage, attempts to reduce stresses through more closely matching the coefficients of thermal expansion of the materials of the lines, dielectric layer, chip and substrate are typically not practical and often inadequate.
The present invention provides a method and structure for reducing mechanical shear stresses induced in an IC chip in the vicinity of metal interconnect lines that interconnect the chip to its surrounding substrate. The invention is applicable to circuit structures having an IC chip supported on the substrate and over which a dielectric layer is deposited to overlie at least a portion of the substrate and a peripheral surface region of the chip. The metal interconnect lines that interconnect the chip to the substrate are formed on the dielectric layer and are electrically interconnected with contact pads on the peripheral surface region of the chip, i.e., beneath the dielectric layer.
According to this invention, at least one trench is formed in the dielectric layer and surrounds the peripheral surface region of the chip. The interconnect lines traverse the trench so as to have nonplanar portions within the trench. The trench and the nonplanar portion of each interconnect line are believed to increase the expansion/contraction capability of the dielectric layer and lines in a region sufficiently close to where the lines are interconnected to the contact pads, such that shear stresses at critical points near the line-pad connections are significantly reduced, thereby reducing the likelihood of fracturing the chip or delaminating the contact pad.
From the above, it can be appreciated that the solution offered by this invention does not rely on an attempt to more closely match the coefficients of thermal expansion of the materials involved. Instead, the invention offers a practical solution for alleviating stress conditions without any requirement for special equipment, exotic materials or complex processing steps. To the contrary, the trenches required by this invention can be formed in the dielectric material using equipment conventionally employed with microelectronic processes, including lasers.
Other objects and advantages of this invention will be better appreciated from the following detailed description.